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CMPE125: Logic Design with Verilog

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Verilog digital logic design with emphasis on ASIC and FPGA design. Students design and verify large-scale systems. Assignments and project use the Verilog Hardware Description Language with emphasis on verification and high-frequency ASIC/FPGA targets. Prerequisite(s): courses 100/L. Concurrent enrollment in course 125L required. Enrollment limited to 40. P. Chan, A. Varma, M. Schlag, J. Renau, M. Guthaus

5 Credits

YearFallWinterSpringSummer
2013-14
  • Section 01
    Staff
2012-13
  • Section 01
    Matthew Guthaus
2011-12
  • Section 01
    Pak K. Chan
2010-11
  • Section 01
    Matthew Guthaus
2009-10
  • Section 01
    Pak K. Chan
2008-09
  • Section 01
    Pak K. Chan
  • Section 01
    Jose Renau
2007-08
  • Section 01
    Anujan Varma
2006-07
  • Section 01
    Matthew Guthaus
2005-06
  • Section 01
    Pak K. Chan
  • Section 01
    Anujan Varma
2004-05
  • Section 01
    Anujan Varma
  • Section 01
    Pak K. Chan
2003-04
  • Section 01
    Anujan Varma
2002-03
  • Section 01
    Pak K. Chan
2001-02
  • Section 01
    Pak K. Chan

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