Logic Design with Verilog

CMPE 125/L Syllabus - Winter 2012
Logic Design with Verilog


Lecture: MW 5pm - 6:45pm, Physical Sciences 110
Lab Section 1: MW 9am - 11am, Baskin 104
Lab Section 2: MW 1pm - 3pm, Baskin 104

Office Hours: M 12-1:30 E2-225

Google Hangout: Tu 11:30-2:30


Verilog digital logic design with emphasis on ASIC and FPGA design. Students design and verify large-scale systems. Assignments and project use the Verilog Hardware Description Language with emphasis on verification and high-frequency ASIC/FPGA targets. Prerequisite(s): courses 100/L. Concurrent enrollment in course 125L required. Enrollment limited to 40.

Some useful resources:

Free Verilog tools:

Instructors and Assistants